Data Structures | Data Fields

SPDINFO::SPECIFICINFO::DDR5SDRAMINFO Struct Reference

DDR5-specific attributes. More...

#include <SysInfo.h>

Data Structures

union  ARFM

Data Fields

float tCKmax
 Maximum clock cycle time in ns.
float tWR
 Write recovery time in ns.
float tRFC2
 Minimum Auto-Refresh to Active/Auto-Refresh Command Period in ns.
float tRFC4
 Minimum Auto-Refresh to Active/Auto-Refresh Command Period in ns.
float tRFC1_dlr
 Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.
float tRFC2_dlr
 Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.
float tRFCsb_dlr
 Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.
union {
   struct {
      unsigned int   baseModuleType: 4
      unsigned int   hybridMedia: 3
      unsigned int   hybrid: 1
   }   bits
   unsigned char   raw
keyByteModuleType
wchar_t moduleType [SHORT_STRING_LEN]
 Module type.
union {
   struct {
      unsigned int   densityPerDie: 5
      unsigned int   diePerPackage: 3
   }   bits
   unsigned char   raw
FirstSDRAMDensityPackage
union {
   struct {
      unsigned int   rowAddrBits: 5
      unsigned int   colAddrBits: 3
   }   bits
   unsigned char   raw
FirstSDRAMAddressing
union {
   struct {
      unsigned int   reserved: 5
      unsigned int   IOWidth: 3
   }   bits
   unsigned char   raw
FirstSDRAMIOWidth
union {
   struct {
      unsigned int   banksPerGroup: 3
      unsigned int   reserved: 2
      unsigned int   bankGroups: 3
   }   bits
   unsigned char   raw
FirstSDRAMBankGroups
union {
   struct {
      unsigned int   densityPerDie: 5
      unsigned int   diePerPackage: 3
   }   bits
   unsigned char   raw
SecondSDRAMDensityPackage
union {
   struct {
      unsigned int   rowAddrBits: 5
      unsigned int   colAddrBits: 3
   }   bits
   unsigned char   raw
SecondSDRAMAddressing
union {
   struct {
      unsigned int   reserved: 5
      unsigned int   IOWidth: 3
   }   bits
   unsigned char   raw
SecondSDRAMIOWidth
union {
   struct {
      unsigned int   banksPerGroup: 3
      unsigned int   reserved: 2
      unsigned int   bankGroups: 3
   }   bits
   unsigned char   raw
SecondSDRAMBankGroups
union {
   struct {
      unsigned int   mPPRhPPRAbort: 1
      unsigned int   MBISTmPPR: 1
      unsigned int   reserved32: 2
      unsigned int   BL32: 1
      unsigned int   sPPRUndoLock: 1
      unsigned int   reserved6: 1
      unsigned int   sPPRGranularity: 1
   }   bits
   unsigned char   raw
BL32PostPackageRepair
union {
   struct {
      unsigned int   DCATypesSupported: 2
      unsigned int   reserved32: 2
      unsigned int   PASR: 1
      unsigned int   reserved75: 3
   }   bits
   unsigned char   raw
DutyCycleAdjusterPartialArraySelfRefresh
union {
   struct {
      unsigned int   BoundedFault: 1
      unsigned int   x4RMWECSWritebackSuppressionMRSelector: 1
      unsigned int   x4RMWECSWritebackSuppression: 1
      unsigned int   reserved73: 5
   }   bits
   unsigned char   raw
FaultHandling
union {
   struct {
      unsigned int   endurant: 2
      unsigned int   operable: 2
      unsigned int   nominal: 4
   }   bits
   unsigned char   raw
NominalVoltageVDD
union {
   struct {
      unsigned int   endurant: 2
      unsigned int   operable: 2
      unsigned int   nominal: 4
   }   bits
   unsigned char   raw
NominalVoltageVDDQ
union {
   struct {
      unsigned int   endurant: 2
      unsigned int   operable: 2
      unsigned int   nominal: 4
   }   bits
   unsigned char   raw
NominalVoltageVPP
union {
   struct {
      unsigned int   RFMRequired: 1
      unsigned int   RAAIMT: 4
      unsigned int   RAAMMT: 3
      unsigned int   reserved: 4
      unsigned int   ARFMLevel: 2
      unsigned int   RFMRAACounterDecrementPerREFcommand: 2
   }   bits
   unsigned char   raw [2]
FirstSDRAMRefreshManagement
union {
   struct {
      unsigned int   RFMRequired: 1
      unsigned int   RAAIMT: 4
      unsigned int   RAAMMT: 3
      unsigned int   reserved: 4
      unsigned int   ARFMLevel: 2
      unsigned int   RFMRAACounterDecrementPerREFcommand: 2
   }   bits
   unsigned char   raw [2]
SecondSDRAMRefreshManagement
union
SPDINFO::SPECIFICINFO::DDR5SDRAMINFO::ARFM 
FirstSDRAMAdaptiveRefreshManagementLevelA
union ARFM FirstSDRAMAdaptiveRefreshManagementLevelB
union ARFM FirstSDRAMAdaptiveRefreshManagementLevelC
union ARFM SecondSDRAMAdaptiveRefreshManagementLevelA
union ARFM SecondSDRAMAdaptiveRefreshManagementLevelB
union ARFM SecondSDRAMAdaptiveRefreshManagementLevelC
int moduleSPDRev
 SPD revision.
struct {
   DEVINFO   SPD
   DEVINFO   PMIC0
   DEVINFO   PMIC1
   DEVINFO   PMIC2
   DEVINFO   ThermalSensors
moduleDeviceInfo
int moduleHeight
 Module height.
int moduleThicknessFront
 Module thickness (front).
int moduleThicknessBack
 Module thickness (back).
union {
   struct {
      unsigned int   ReferenceDesign: 5
      unsigned int   DesignRevision: 3
   }   bits
   unsigned char   raw
ReferenceRawCardUsed
wchar_t moduleRefCard [SHORT_STRING_LEN]
 Reference raw card used.
unsigned char DRAMManufID
 DRAM manufacture ID.
int DRAMManufBank
 DRAM manufacture bank.
wchar_t DRAMManuf [SHORT_STRING_LEN]
 DRAM manufacture name.
int DRAMStepping
 DRAM Stepping.
union {
   struct {
      unsigned int   NumDRAMRows: 2
      unsigned int   HeatSpreader: 1
      unsigned int   reserved: 1
      unsigned int   OperatingTemperatureRange: 4
   }   bits
   unsigned char   raw
DIMMAttributes
union {
   struct {
      unsigned int   reserved20: 3
      unsigned int   NumPackageRanksPerChannel: 3
      unsigned int   RankMix: 1
      unsigned int   reserved7: 1
   }   bits
   unsigned char   raw
ModuleOrganization
union {
   struct {
      unsigned int   PrimaryBusWidthPerChannel: 3
      unsigned int   BusWidthExtensionPerChannel: 2
      unsigned int   NumChannelsPerDIMM: 2
      unsigned int   reserved: 1
   }   bits
   unsigned char   raw
MemoryChannelBusWidth
union {
   struct {
      DEVINFO   RegisteringClockDriver
      DEVINFO   DataBuffers
      union {
         struct {
            unsigned int   QACK_tQACK_c: 1
            unsigned int   QBCK_tQBCK_c: 1
            unsigned int   QCCK_tQCCK_c: 1
            unsigned int   QDCK_tQDCK_c: 1
            unsigned int   reserved4: 1
            unsigned int   BCK_tBCK_c: 1
            unsigned int   reserved76: 2
         }   bits
         unsigned char   raw
      }   RCDRW08ClockDriverEnable
      union {
         struct {
            unsigned int   QACAOutputs: 1
            unsigned int   QBCAOutputs: 1
            unsigned int   DCS1_nInputBufferQxCS1_nOutputs: 1
            unsigned int   BCS_nBCOM20BRST_nOutputs: 1
            unsigned int   QBACA13OutputDriver: 1
            unsigned int   QACS10_nOutput: 1
            unsigned int   QBCS10_nOutput: 1
            unsigned int   reserved: 1
         }   bits
         unsigned char   raw
      }   RCDRW09OutputAddressControlEnable
      union {
         struct {
            unsigned int   QACK_tQACK_c: 2
            unsigned int   QBCK_tQBCK_c: 2
            unsigned int   QCCK_tQCCK_c: 2
            unsigned int   QDCK_tQDCK_c: 2
         }   bits
         unsigned char   raw
      }   RCDRW0AQCKDriverCharacteristics
      union {
         struct {
            unsigned int   reserved: 8
         }   bits
         unsigned char   raw
      }   RCDRW0B
      union {
         struct {
            unsigned int   DriverStrengthAddressCommandABOutputs: 2
            unsigned int   reserved32: 2
            unsigned int   DriverStrengthQxCS0_nQxCS1_nQCCK_tQCCK_c: 2
            unsigned int   reserved76: 2
         }   bits
         unsigned char   raw
      }   RCDRW0CQxCAQxCS_nDriverCharacteristics
      union {
         struct {
            unsigned int   DriverStrengthBCOM20BCS_n: 2
            unsigned int   reserved2: 1
            unsigned int   DriverStrengthBCK_tBCK_c: 2
            unsigned int   reserved75: 3
         }   bits
         unsigned char   raw
      }   RCDRW0DDataBufferInterfaceDriverCharacteristics
      union {
         struct {
            unsigned int   QCKDA_tQCKDA_cDifferentialSlewRate: 2
            unsigned int   QBACA130SingleEndedSlewRate: 2
            unsigned int   QBACS10_nSingleEndedSlewRate: 2
            unsigned int   reserved76: 2
         }   bits
         unsigned char   raw
      }   RCDRW0EQCKQCAQCOutputSlewRate
      union {
         struct {
            unsigned int   BCOM20BCS_nSingleEndedSlewRate: 2
            unsigned int   BCK_tBCK_cDifferentialSlewRate: 2
            unsigned int   reserved74: 4
         }   bits
         unsigned char   raw
      }   RCDRW0FBCKBCOMBCSOutputSlewRate
      union {
         struct {
            unsigned int   DQSRTTParkTermination: 3
            unsigned int   reserved73: 5
         }   bits
         unsigned char   raw
      }   DBRW86DQSRTTParkTermination
   }   RDIMM
   struct {
      DEVINFO   DifferentialMemoryBuffer
   }   DDIMM
   struct {
      DEVINFO   RegisteringClockDriver
      DEVINFO   DataBuffers
   }   NVDIMMN
   struct {
      DEVINFO   RegisteringClockDriver
      DEVINFO   DataBuffers
   }   NVDIMMP
baseModule
unsigned short BaseCfgCRC16
 Cyclical Redundancy Code (CRC) for Base Configuration Section.
bool XMPSupported
 TRUE if Intel Extreme Memory Profile (XMP) supported.
struct {
   unsigned char   version
 Intel Extreme Memory Profile Version.
   unsigned char   PMICVendorID [2]
 PMIC Vendor ID.
   int   numPMIC
 Number of PMICs.
   union {
      struct {
         unsigned int   OCCapable: 1
         unsigned int   OCEnable: 1
         unsigned int   VoltageDefaultStepSize: 1
         unsigned int   OCGlobalResetEnable: 1
         unsigned int   reserved75: 3
      }   bits
      unsigned char   raw
   }   PMICCapabilities
 PMIC Capabilities.
   union {
      struct {
         unsigned int   SelfCertified: 1
         unsigned int   PMICIntelAVLValidated: 1
         unsigned int   reserved72: 6
      }   bits
      unsigned char   raw
   }   ValidationCertification
 Validation and Certification Capabilities.
   unsigned char   revision
 Intel Extreme Memory Profile Spec Revision.
   unsigned short   BaseCfgCRC16
 Cyclical Redundancy Code (CRC) for Base Configuration Section.
   struct {
      bool   enabled
 TRUE if this profile contains valid data.
      int   certified
 0 if this profile is XMP ready, 1 if this profile is XMP certified
      int   dimmsPerChannel
 Recommended number of DIMMs per channel.
      char   name [SHORT_STRING_LEN]
 Profile string name.
      wchar_t   moduleVPP [SHORT_STRING_LEN]
 Module VPP Voltage Level.
      wchar_t   moduleVDD [SHORT_STRING_LEN]
 Module VDD Voltage Level.
      wchar_t   moduleVDDQ [SHORT_STRING_LEN]
 Module VDDQ Voltage Level.
      wchar_t   memCtrlVoltage [SHORT_STRING_LEN]
 Memory Controller Voltage Level.
      float   clkspeed
 Clock speed in MHz.
      wchar_t   CASSupported [SHORT_STRING_LEN]
 CAS latencies supported.
      float   tCK
 Minimum clock cycle time in ns.
      float   tAA
 Minimum CAS latency time in ns.
      float   tRCD
 Minimum RAS to CAS delay in ns.
      float   tRP
 Minimum Row Precharge time in ns.
      float   tRAS
 Minimum Active to Precharge Time in ns.
      float   tRC
 Minimum Auto-Refresh to Active/Auto-Refresh Time in ns.
      float   tWR
 Minimum Write Recovery Time in ns.
      float   tRFC1
 SDRAM Minimum Refresh Recovery Delay Time in ns.
      float   tRFC2
 SDRAM Minimum Refresh Recovery Delay Time in ns.
      float   tRFCsb
 SDRAM Minimum Refresh Recovery Delay Time in ns.
      float   tCCD_L
 SDRAM Minimum Read to Read Command Delay Time, Same Bank Group in ns.
      int   tCCD_L_nCK
 SDRAM Minimum Read to Read Command Delay Time, Same Bank Group in nCK.
      float   tCCD_L_WR
 SDRAM Minimum Write to Write Command Delay Time, Same Bank Group in ns.
      int   tCCD_L_WR_nCK
 SDRAM Minimum Write to Write Command Delay Time, Same Bank Group in nCK.
      float   tCCD_L_WR2
 SDRAM Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group in ns.
      int   tCCD_L_WR2_nCK
 SDRAM Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group in nCK.
      float   tCCD_L_WTR
 SDRAM Minimum Write to Read Command Delay Time, Same Bank Group in ns.
      int   tCCD_L_WTR_nCK
 SDRAM Minimum Write to Read Command Delay Time, Same Bank Group in nCK.
      float   tCCD_S_WTR
 SDRAM Minimum Write to Read Command Delay Time, Different Bank Group in ns.
      int   tCCD_S_WTR_nCK
 SDRAM Minimum Write to Read Command Delay Time, Different Bank Group in nCK.
      float   tRRD_L
 SDRAM Minimum Active to Active Command Delay Time, Same Bank Group in ns.
      int   tRRD_L_nCK
 SDRAM Minimum Active to Active Command Delay Time, Same Bank Group in nCK.
      float   tRTP
 SDRAM Minimum Read to Precharge Command Delay Time in ns.
      int   tRTP_nCK
 SDRAM Minimum Read to Precharge Command Delay Time in nCK.
      float   tFAW
 SDRAM Minimum Four Activate Window in ns.
      int   tFAW_nCK
 SDRAM Minimum Four Activate Window in nCK.
      union {
         struct {
            unsigned int   RealTimeMemoryFrequencyOverclocking: 1
            unsigned int   IntelDynamicMemoryBoost: 1
            unsigned int   reserved72: 6
         }   bits
         unsigned char   raw
      }   AdvancedMemoryOverclockingFeatures
 Advanced Memory Overclocking Features.
      int   cmdRateMode
 System CMD Rate Mode.
      unsigned char   VendorPersonalityByte
 Vendor Personality Byte.
      unsigned short   BaseCfgCRC16
 Cyclical Redundancy Code (CRC) for Base Configuration Section.
   }   profile [MAX_XMP3_PROFILES]
 XMP profile attributes.
XMP
 XMP-specific attributes.

Detailed Description

DDR5-specific attributes.


Field Documentation

float tCKmax

Maximum clock cycle time in ns.

float tWR

Write recovery time in ns.

Minimum Write Recovery Time in ns.

float tRFC2

Minimum Auto-Refresh to Active/Auto-Refresh Command Period in ns.

SDRAM Minimum Refresh Recovery Delay Time in ns.

float tRFC4

Minimum Auto-Refresh to Active/Auto-Refresh Command Period in ns.

float tRFC1_dlr

Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.

float tRFC2_dlr

Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.

float tRFCsb_dlr

Minimum Refresh Recovery Delay Time, 3DS Different Logical Rank in ns.

unsigned int baseModuleType
unsigned int hybridMedia
unsigned int hybrid
struct { ... } bits
unsigned char raw
union { ... } keyByteModuleType
wchar_t moduleType[SHORT_STRING_LEN]

Module type.

unsigned int densityPerDie
unsigned int diePerPackage
struct { ... } bits
union { ... } FirstSDRAMDensityPackage
unsigned int rowAddrBits
unsigned int colAddrBits
struct { ... } bits
union { ... } FirstSDRAMAddressing
unsigned int reserved
unsigned int IOWidth
struct { ... } bits
union { ... } FirstSDRAMIOWidth
unsigned int banksPerGroup
unsigned int bankGroups
struct { ... } bits
union { ... } FirstSDRAMBankGroups
struct { ... } bits
struct { ... } bits
union { ... } SecondSDRAMAddressing
struct { ... } bits
union { ... } SecondSDRAMIOWidth
struct { ... } bits
union { ... } SecondSDRAMBankGroups
unsigned int mPPRhPPRAbort
unsigned int MBISTmPPR
unsigned int reserved32
unsigned int BL32
unsigned int sPPRUndoLock
unsigned int reserved6
unsigned int sPPRGranularity
struct { ... } bits
union { ... } BL32PostPackageRepair
unsigned int DCATypesSupported
unsigned int PASR
unsigned int reserved75
struct { ... } bits
unsigned int BoundedFault
unsigned int reserved73
struct { ... } bits
union { ... } FaultHandling
unsigned int endurant
unsigned int operable
unsigned int nominal
struct { ... } bits
union { ... } NominalVoltageVDD
struct { ... } bits
union { ... } NominalVoltageVDDQ
struct { ... } bits
union { ... } NominalVoltageVPP
unsigned int RFMRequired
unsigned int RAAIMT
unsigned int RAAMMT
unsigned int ARFMLevel
struct { ... } bits
struct { ... } bits

SPD revision.

struct { ... } moduleDeviceInfo

Module height.

Module thickness (front).

Module thickness (back).

unsigned int ReferenceDesign
unsigned int DesignRevision
struct { ... } bits
union { ... } ReferenceRawCardUsed
wchar_t moduleRefCard[SHORT_STRING_LEN]

Reference raw card used.

unsigned char DRAMManufID

DRAM manufacture ID.

DRAM manufacture bank.

wchar_t DRAMManuf[SHORT_STRING_LEN]

DRAM manufacture name.

DRAM Stepping.

unsigned int NumDRAMRows
unsigned int HeatSpreader
struct { ... } bits
union { ... } DIMMAttributes
unsigned int reserved20
unsigned int RankMix
unsigned int reserved7
struct { ... } bits
union { ... } ModuleOrganization
unsigned int NumChannelsPerDIMM
struct { ... } bits
union { ... } MemoryChannelBusWidth
unsigned int QACK_tQACK_c
unsigned int QBCK_tQBCK_c
unsigned int QCCK_tQCCK_c
unsigned int QDCK_tQDCK_c
unsigned int reserved4
unsigned int BCK_tBCK_c
unsigned int reserved76
struct { ... } bits
union { ... } ::@54 RCDRW08ClockDriverEnable
unsigned int QACAOutputs
unsigned int QBCAOutputs
unsigned int QBACA13OutputDriver
unsigned int QACS10_nOutput
unsigned int QBCS10_nOutput
struct { ... } bits
union { ... } ::@55 RCDRW09OutputAddressControlEnable
struct { ... } bits
union { ... } ::@56 RCDRW0AQCKDriverCharacteristics
struct { ... } bits
union { ... } ::@57 RCDRW0B
struct { ... } bits
unsigned int reserved2
struct { ... } bits
struct { ... } bits
union { ... } ::@60 RCDRW0EQCKQCAQCOutputSlewRate
unsigned int reserved74
struct { ... } bits
union { ... } ::@61 RCDRW0FBCKBCOMBCSOutputSlewRate
unsigned int DQSRTTParkTermination
struct { ... } bits
union { ... } ::@62 DBRW86DQSRTTParkTermination
struct { ... } RDIMM
struct { ... } DDIMM
struct { ... } NVDIMMN
struct { ... } NVDIMMP
union { ... } baseModule
unsigned short BaseCfgCRC16

Cyclical Redundancy Code (CRC) for Base Configuration Section.

TRUE if Intel Extreme Memory Profile (XMP) supported.

unsigned char version

Intel Extreme Memory Profile Version.

unsigned char PMICVendorID[2]

PMIC Vendor ID.

int numPMIC

Number of PMICs.

unsigned int OCCapable
unsigned int OCEnable
unsigned int VoltageDefaultStepSize
unsigned int OCGlobalResetEnable
struct { ... } ::@75 bits
union { ... } PMICCapabilities

PMIC Capabilities.

unsigned int SelfCertified
unsigned int PMICIntelAVLValidated
unsigned int reserved72
struct { ... } ::@76 bits
union { ... } ValidationCertification

Validation and Certification Capabilities.

unsigned char revision

Intel Extreme Memory Profile Spec Revision.

bool enabled

TRUE if this profile contains valid data.

int certified

0 if this profile is XMP ready, 1 if this profile is XMP certified

Recommended number of DIMMs per channel.

char name[SHORT_STRING_LEN]

Profile string name.

wchar_t moduleVPP[SHORT_STRING_LEN]

Module VPP Voltage Level.

wchar_t moduleVDD[SHORT_STRING_LEN]

Module VDD Voltage Level.

wchar_t moduleVDDQ[SHORT_STRING_LEN]

Module VDDQ Voltage Level.

wchar_t memCtrlVoltage[SHORT_STRING_LEN]

Memory Controller Voltage Level.

float clkspeed

Clock speed in MHz.

wchar_t CASSupported[SHORT_STRING_LEN]

CAS latencies supported.

float tCK

Minimum clock cycle time in ns.

float tAA

Minimum CAS latency time in ns.

float tRCD

Minimum RAS to CAS delay in ns.

float tRP

Minimum Row Precharge time in ns.

float tRAS

Minimum Active to Precharge Time in ns.

float tRC

Minimum Auto-Refresh to Active/Auto-Refresh Time in ns.

float tRFC1

SDRAM Minimum Refresh Recovery Delay Time in ns.

float tRFCsb

SDRAM Minimum Refresh Recovery Delay Time in ns.

float tCCD_L

SDRAM Minimum Read to Read Command Delay Time, Same Bank Group in ns.

SDRAM Minimum Read to Read Command Delay Time, Same Bank Group in nCK.

float tCCD_L_WR

SDRAM Minimum Write to Write Command Delay Time, Same Bank Group in ns.

SDRAM Minimum Write to Write Command Delay Time, Same Bank Group in nCK.

float tCCD_L_WR2

SDRAM Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group in ns.

SDRAM Minimum Write to Write Command Delay Time, Second Write not RMW, Same Bank Group in nCK.

float tCCD_L_WTR

SDRAM Minimum Write to Read Command Delay Time, Same Bank Group in ns.

SDRAM Minimum Write to Read Command Delay Time, Same Bank Group in nCK.

float tCCD_S_WTR

SDRAM Minimum Write to Read Command Delay Time, Different Bank Group in ns.

SDRAM Minimum Write to Read Command Delay Time, Different Bank Group in nCK.

float tRRD_L

SDRAM Minimum Active to Active Command Delay Time, Same Bank Group in ns.

SDRAM Minimum Active to Active Command Delay Time, Same Bank Group in nCK.

float tRTP

SDRAM Minimum Read to Precharge Command Delay Time in ns.

int tRTP_nCK

SDRAM Minimum Read to Precharge Command Delay Time in nCK.

float tFAW

SDRAM Minimum Four Activate Window in ns.

int tFAW_nCK

SDRAM Minimum Four Activate Window in nCK.

struct { ... } bits

Advanced Memory Overclocking Features.

System CMD Rate Mode.

unsigned char VendorPersonalityByte

Vendor Personality Byte.

struct { ... } profile[MAX_XMP3_PROFILES]

XMP profile attributes.

struct { ... } XMP

XMP-specific attributes.


The documentation for this struct was generated from the following file:
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